The present disclosure relates generally an integrated circuit device and, more particularly, a method of patterning a gate structure of an IC device.
As technology nodes decrease, semiconductor fabrication processes have introduced the use of gate dielectric materials having a high dielectric constant (e.g., high-k dielectrics). The high-k dielectrics exhibit a higher dielectric constant than the traditionally used silicon dioxide which allows for thicker dielectric layers to be used to obtain similar equivalent oxide thicknesses (EOTs). The processes also benefit from the introduction of metal gate structures providing a lower resistance than the traditional polysilicon gate structures.
However, the fabrication processes providing for use of a high-k dielectric plus metal gate structure face challenges. For example, problems arise in using conventional photolithography techniques to pattern high-k metal gate structures. Traditional methods to remove masking elements (e.g., dry ash and wet etch processes to remove photoresist) may damage the underlying high-k gate dielectric film and/or the metal gate films. Furthermore, the formation of a photoresist feature directly on a metal film which is to be patterned may raise challenges. For example, photoresist peeling may occur due to poor adhesion between the photoresist and metal.
Therefore, what is needed is an improved method of patterning a metal gate structure.